Sample makefile

Here is a quick little makefile I use in small projects. It compiles all *.cpp files, and then links all *.o files into a single binary. It also includes a nice “list” target, which lists all the available targets. I realize bash tab auto-complete usually is good enough, but for programmatic uses, make list is helpful.

# references:
#    BUILD_DIR and per-.cpp file https://spin.atomicobject.com/2016/08/26/makefile-c-projects/
awkbin     :=$(shell which awk)
cpbin      :=$(shell which cp)
echobin    :=$(shell which echo)
findbin    :=$(shell which find)
grepbin    :=$(shell which grep)
installbin :=$(shell which install)
rmbin      :=$(shell which rm)
sedbin     :=$(shell which sed)
sortbin    :=$(shell which sort)
truebin    :=$(shell which true)

CXX = g++

# to get full debug symbols, add to both FLAGS: -g
# to make all warnings act as errors: -Wall -Weffc++ -Wextra -Wsign-conversion -Werror
CXXFLAGS = -g -std=c++17 -Wall -Weffc++ -Wextra -Wsign-conversion -Werror

# to remove all debug symbols: -s
# to add full debug symbols: -g
LDFLAGS = -g

src = $(wildcard *.cpp)
obj = $(src:.cpp=.o)

BUILD_DIR ?= .

OUTEXE = mine

all: $(OUTEXE)

# compile, which is not actually used?
$(BUILD_DIR)%.o: %.cpp
	$(CXX) -c $(CXXFLAGS) $+

# link
$(OUTEXE): $(obj)
	$(CXX) -o $@ $^ $(LDFLAGS)

.PHONY: clean cleanall list

list:
	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | ${awkbin} -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | ${sortbin} | ${grepbin} -E -v -e '^[^[:alnum:]]' -e '^$@$$' -e '\.(cp*|o)'

clean:
	rm -f $(obj)

cleanall:
	rm -f $(obj) $(OUTEXE)

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